Various processes such as a film formation, an etching and the like are repeatedly performed on a semiconductor wafer to manufacture a desired semiconductor device. Recently, in order to meet demands for high-speed semiconductor device, miniaturization of a wiring pattern and high level of integration, it is required to realize low resistance of wiring (high conductivity) and high electromigration resistance.
Accordingly, copper (Cu) having a higher electromigration resistance and a higher conductivity (lower resistance) than Al or W has been used as a wiring material.
As for the Cu wiring forming method, there has been proposed a technique including: forming a barrier film formed of tantalum metal (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN) or the like on an entire interlayer insulating film having a trench or a hole by a plasma sputtering as an example of a physical vapor deposition (PVD); forming a Cu seed film on the barrier film by the plasma sputtering; filling the trench or the hole by performing a Cu plating process; and removing a residual Cu thin film or a residual barrier film remaining on the wafer surface by a chemical mechanical polishing (CMP) (see, e.g., Japanese Patent Application Publication No. 2006-148075).
However, as a design rule for scaling-down of the aformendtioned semiconductor device progresses, a hole diameter or a width of a trench has reached several tens of nm, and the formation of a Cu wiring in a recess such as a narrow trench or a narrow hole leads to an increase of a wiring resistance. Further, when the trench or the hole is filled by performing the Cu plating process after the barrier film and/or the seed film are formed by the plasma sputtering as described in Japanese Patent Application Publication No. 2006-148075, the recess may not be completely filled up (poor fillability), which results in a generation of a void.